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Cadence says its AI-driven chip design tools provide a process node's worth of performance gain, but without moving forward to a new node
Anirudh Devgan, the CEO of Cadence, recently remarked that the company's AI-assisted chip design tools enable chip ... verification, PCB and package and system analysis, it is a pretty rich ...
Electronics Weekly1d
UKESF adds Cadence Trustee to strengthen Board
Madhuparna Datta, of Cadence Design Systems, joins the UK Electronics Skill Foundation's (UKESF) board as a Trustee.
Design-Reuse8y
Faraday Reduces Packaging Design Time by 60 Percent Using Cadence OrbitIO Interconnect Designer and SiP Layout
OrbitIO interconnect designer capabilities deliver hierarchical multi-substrate-optimized design for SoCs and ASICs across IC package/SiP and systems San Jose, Calif., 04 May 2016 -- Cadence Design ...