That makes the placement & optimization process clock aware. Also it provide the necessary pull/push information for clock logic while clock tree building. Clock Gate Aware Design Closure Algorithm ...

The status is fed back as part of the logic inputs. When the clock signal rises ... the logic behaviour but does not take delays in the wires or the gates, dependencies of supply voltage, temperature, ...

A collection of transistors and resistors that implement Boolean logic operations in a digital circuit. Logic gates have one or two 0 or 1 inputs but only one 0 or 1 output as in the following ...